Docsity
Log inSign up
Docsity
Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity

Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan

Guidelines and tips
Guidelines and tips
Sell on Docsity
Sell on Docsity
Log inSign up

Prepare for your exams

Study with the several resources on Docsity

Find documents

Prepare for your exams with the study notes shared by other students like you on Docsity

Search Store documents

The best documents sold by students who completed their studies

Search through all study resources
Docsity AINEW

Summarize your documents, ask them questions, convert them into quizzes and concept maps

Explore questions

Clear up your doubts by reading the answers to questions asked by your fellow students

Earn points to download

Earn points by helping other students or get them with a premium plan

Share documents
download point icon20 Points

For each uploaded document

Answer questions
download point icon5 Points

For each given answer (max 1 per day)

All the ways to get free points
Get points immediately

Choose a premium plan with all the points you need

Study Opportunities

Choose your next study program

Get in touch with the best universities in the world. Search through thousands of universities and official partners

Community

Ask the community

Ask the community for help and clear up your study doubts

University Rankings

Discover the best universities in your country according to Docsity users

Free resources

Our save-the-student-ebooks!

Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors

From our blog

Exams and Study
Go to the blog

Week‐3 Assignment, Exercises of Programming Languages

Henderson State University (HSU)Programming Languages

10 multiple choice questions unsolved.

Typology: Exercises

2021/2022

Uploaded on 03/31/2022

jamal33
jamal33 🇺🇸

4.3

(50)

341 documents

1 / 3

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
Week‐3
AssignmentQuestionsandAnswers
1. Netlistisa______representationofacircuit.
a. graphic
b. text‐based
c. handwritten
d. pictorial
2. RTLstandsfor_____________.
a. resistor‐transferlogic
b. register‐transistorlogic
c. register‐transferlogic
d. noneofthese
3. VerilogHDLoriginatedat
a. AT&TBelllaboratories
b. DefenseAdvancedResearchProjectsAgency(DARPA)
c. GatewayDesignAutomation
d. InstituteofElectricalandElectronicsEngineers(IEEE)
4. Statewhetherthefollowingstatementsaretrueorfalse:
a. Verilogiscasesensitive.
i. True
ii. False
b. “beginmodule”and“endmodule”arereservedwordsinVerilog.
i. True
ii. False
c. Thesemanticsofan“&”operatordependsonthenumberofoperands.
i. True
ii. False
d. An“if”statementmustalwaysbeinsideofan“always”block.
i. True
ii. False
pf3

Partial preview of the text

Download Week‐3 Assignment and more Exercises Programming Languages in PDF only on Docsity!

Week‐ 3

Assignment Questions and Answers

  1. Netlist is a ______ representation of a circuit. a. graphic b. text‐based c. handwritten d. pictorial
  2. RTL stands for _____________. a. resistor‐transfer logic b. register‐transistor logic c. register‐transfer logic d. none of these
  3. Verilog HDL originated at a. AT&T Bell laboratories b. Defense Advanced Research Projects Agency(DARPA) c. Gateway Design Automation d. Institute of Electrical and Electronics Engineers(IEEE)
  4. State whether the following statements are true or false: a. Verilog is case sensitive. i. True ii. False

b. “ beginmodule ” and “ endmodule ” are reserved words in Verilog. i. True ii. False

c. The semantics of an “&” operator depends on the number of operands. i. True ii. False

d. An “ if ” statement must always be inside of an “ always ” block. i. True ii. False

e. Verilog may be written at the Behavioral, Structural, Gate, Switch, and Transistor levels. i. True ii. False

f. The use of a tick timescale (‘timescale) enables code to be synthesized with the

specified delays.

i. True ii. False

g. Use of Blocking Assignments is preferable to Non-Blocking Assignments

because race conditions are less likely to occur.

i. True ii. False

h. Verilog permits module ports to be unconnected.

i. True ii. False

  1. Which of the following is(are) equivalent to logic level 1? a. 1 b. 1’b c. 1 ‘b d. a and b e. a, b and c

6. Which of the following is true about parameters?

a. The default size of a parameter in most synthesizers is the size of an integer, 32 bits.

b. Parameters enable Verilog code to be compatible with VHDL.

c. Parameters cannot accept a default value.

d. All of the above.

e. None of the above

7. Which of following tool/tools can be used to synthesize and implement a digital circuit

on a Nexys 4 DDR board?

a. Quartus Prime

b. Xilinx ISE

c. Vivado

d. a and c

e. b and c