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VHDL Operators, Functions, Procedures, and Signal Attributes in Advanced Logic Design, Study notes of Electrical and Electronics Engineering

University of Alabama - HuntsvilleElectrical and Electronics Engineering

Various aspects of vhdl in the context of advanced logic design, including operators, functions, procedures, and signal attributes. It includes detailed explanations and examples of vhdl operators, the use of functions and procedures for code decomposition and error checking, and the attributes associated with signals that return a value or create a signal. The document also discusses array attributes, transport and inertial delay, operator overloading, multivalued logic, and the ieee 1164 standard logic system.

Typology: Study notes

Pre 2010

Uploaded on 07/22/2009

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CPE/EE 422/522
Advanced Logic Design
L11
Electrical and Computer Engineering
University of Alabama in Huntsville
01/07/2003 UAH-CPE/EE 422/522 AM 2
Outline
•What we know
–How to model Combinational Networks in VHDL
•Structural, Dataflow, Behavioral
–How to model Flip-flops in VHDL
–Processes
–Delays (delta, transport, inertial)
–How to model FSM in VHDL
–Wait statements
–Variables, Signals, Arrays
•What we do not know
–VHDL Operators
–Procedures, Functions
–Packages, Libraries
–Additional Topics (if time)
01/07/2003 UAH-CPE/EE 422/522 AM 3
Review: VHDL Operators
1. Binary logical operators: and or nand nor xor xnor
2. Relational: = /= < <= > >=
3. Shift: sll srl sla sra rol ror
4. Adding: + -& (concatenation)
5. Unary sign: + -
6. Multiplying: * / mod rem
7. Miscellaneous: not abs **
•Class 7 has the highest precedence (applied first),
followed by class 6, then class 5, etc
01/07/2003 UAH-CPE/EE 422/522 AM 4
Example of VHDL Operators
01/07/2003 UAH-CPE/EE 422/522 AM 5
Example of Shift Operators
01/07/2003 UAH-CPE/EE 422/522 AM 6
VHDL Functions
•Functions execute a sequential algorithm and
return a single value to calling program
•A = “10010101”
•General form
pf3
pf4
pf5
pf8

Partial preview of the text

Download VHDL Operators, Functions, Procedures, and Signal Attributes in Advanced Logic Design and more Study notes Electrical and Electronics Engineering in PDF only on Docsity!

CPE/EE 422/

Advanced Logic Design

L

Electrical and Computer Engineering

University of Alabama in Huntsville

01/07/2003 UAH-CPE/EE 422/522 AM 2

Outline

  • What we know
    • How to model Combinational Networks in VHDL
      • Structural, Dataflow, Behavioral
    • How to model Flip-flops in VHDL
    • Processes
    • Delays (delta, transport, inertial)
    • How to model FSM in VHDL
    • Wait statements
    • Variables, Signals, Arrays
  • What we do not know
    • VHDL Operators
    • Procedures, Functions
    • Packages, Libraries
    • Additional Topics (if time)
01/07/2003 UAH-CPE/EE 422/522 AM 3

Review: VHDL Operators

  1. Binary logical operators: and or nand nor xor xnor
  2. Relational: = /= < <= > >=
  3. Shift: sll srl sla sra rol ror
  4. Adding: + - & (concatenation)
  5. Unary sign: + -
  6. Multiplying: * / mod rem
  7. Miscellaneous: not abs **
  • Class 7 has the highest precedence (applied first),

followed by class 6, then class 5, etc

01/07/2003 UAH-CPE/EE 422/522 AM 4

Example of VHDL Operators

01/07/2003 UAH-CPE/EE 422/522 AM 5

Example of Shift Operators

01/07/2003 UAH-CPE/EE 422/522 AM 6

VHDL Functions

  • Functions execute a sequential algorithm and

return a single value to calling program

  • A = “10010101”
  • General form
01/07/2003 UAH-CPE/EE 422/522 AM 7

For Loops

01/07/2003 UAH-CPE/EE 422/522 AM 8

Add Function

01/07/2003 UAH-CPE/EE 422/522 AM 9

VHDL Procedures

  • Facilitate decomposition of VHDL code into modules
  • Procedures can return any number of values

using output parameters

procedure_name (actual-parameter-list);

  • General form

procedure procedure_name (formal -parameter-list) is

[declarations]

begin

Sequential-statements

end procedure_name;

01/07/2003 UAH-CPE/EE 422/522 AM 10

Procedure for Adding Bit_vectors

01/07/2003 UAH-CPE/EE 422/522 AM 11

Parameters for Subprogram Calls

01/07/2003 UAH-CPE/EE 422/522 AM 12

Packages and Libraries

  • Provide a convenient way of referencing

frequently used functions and components

  • Package declaration
  • Package body [optional]
01/07/2003 UAH-CPE/EE 422/522 AM 19

Cascaded Counters (cont’d)

01/07/2003 UAH-CPE/EE 422/522 AM 20

Additional Topics in VHDL

  • Attributes
  • Transport and Inertial Delays
  • Operator Overloading
  • Multivalued Logic and Signal Resolution
  • IEEE 1164 Standard Logic
  • Generics
  • Generate Statements
  • Synthesis of VHDL Code
  • Synthesis Examples
  • Files and Text IO
01/07/2003 UAH-CPE/EE 422/522 AM 21

Signal Attributes

Attributes associated with signals

that return a value

A’event – true if a change in S has just occurred

A’active – true if A has just been reevaluated, even if A does not change

01/07/2003 UAH-CPE/EE 422/522 AM 22

Signal Attributes (cont’d)

  • Event
    • occurs on a signal every time it is changed
  • Transaction
    • occurs on a signal every time it is evaluated
  • Example:

A <= B - - B changes at time T

A’event
T + 1d
T
B’event
01/07/2003 UAH-CPE/EE 422/522 AM 23

Signal Attributes (cont’d)

entity test is
end;
architecture bmtest of test is
signal A : bit;
signal B : bit;
signal C : bit;
begin
A <= not A after 20 ns;
B <= '1';
C <= A and B;

process(A, B, C) variable Aev : bit; variable Aac : bit; variable Bev : bit; variable Bac : bit; variable Cev : bit; variable Cac : bit;

begin if (A'event) then Aev := '1'; else Aev := '0'; end if; if (A'active) then A a c := '1'; else Aac := '0'; end if; if (B'event) then Bev := '1'; else Bev := '0'; end if; if (B'active) then B a c := '1'; else Bac := '0'; end if; if (C'event) then Cev := '1'; else Cev := '0'; end if; if (C'active) then C a c := '1'; else Cac := '0'; end if;

end process;

end bmtest; 01/07/2003 UAH-CPE/EE 422/522 AM 24

Signal Attributes (cont’d)

ns /test/a /test/line__15/bev
delta /test/b /test/line__15/ bac
/test/c /test/line__15/cev
/test/line__15/aev /test/line__15/ cac
/test/line__15/ aac
01/07/2003 UAH-CPE/EE 422/522 AM 25

Signal Attributes (cont’d)

Attributes that create a signal

01/07/2003 UAH-CPE/EE 422/522 AM 26

Examples of Signal Attributes

01/07/2003 UAH-CPE/EE 422/522 AM 27

Using Attributes for Error Checking

check: process
begin
wait until rising_edge(Clk );
assert (D’stable(setup_time))
report(“Setup time violation”)
severity error;
wait for hold_time;
assert (D’stable(hold_time))
report(“Hold time violation”)
severity error;
end process check;
01/07/2003 UAH-CPE/EE 422/522 AM 28

Array Attributes

A can be either an array name or an array type.
Array attributes work with signals, variables, and constants.
01/07/2003 UAH-CPE/EE 422/522 AM 29

Recap: Adding Vectors

Note: Add1 and Add2 vectors must be dimensioned as N-1 downto 0.
Use attributes to write more general procedure that places
no restrictions on the range of vectors other than the lengths m ust be same.
01/07/2003 UAH-CPE/EE 422/522 AM 30

Procedure for Adding Bit Vectors

01/07/2003 UAH-CPE/EE 422/522 AM 37

Tristate Buffers

Resolution function to

determine the actual

value of f since it is

driven from two different

sources

01/07/2003 UAH-CPE/EE 422/522 AM 38

Signal Resolution

  • VHDL signals may either be

resolved or unresolved

  • Resolved signals have an associated

resolution function

  • Bit type is unresolved –
    • there is no resolution function
    • if you drive a bit signal to two different values

in two concurrent statements,

the compiler will generate an error

01/07/2003 UAH-CPE/EE 422/522 AM 39

Signal Resolution (cont’d)

signal R : X01Z := ‘Z’; ...
R <= transport ‘0’ after 2 ns, ‘Z’ after 6 ns;
R <= transport ‘1’ after 4 ns;
R <= transport ‘1’ after 8 ns, ‘0’ after 10 ns;
01/07/2003 UAH-CPE/EE 422/522 AM 40

Resolution Function for X01Z

Define AND and OR for

4-valued inputs?

01/07/2003 UAH-CPE/EE 422/522 AM 41

AND and OR Functions Using X01Z

‘Z’ ‘X’ ‘0’ ‘X’ ‘X’
‘1’ ‘X’ ‘0’ ‘1’ ‘X’
‘X’ ‘X’ ‘0’ ‘X’ ‘X’
AND ‘X’ ‘0’ ‘1’ ‘Z’
‘Z’ ‘X’ ‘X’ ‘1’ ‘X’
‘0’ ‘X’ ‘0’ ‘1’ ‘X’
‘X’ ‘X’ ‘X’ ‘1’ ‘X’
OR ‘X’ ‘0’ ‘1’ ‘Z’
01/07/2003 UAH-CPE/EE 422/522 AM 42

IEEE 1164 Standard Logic

  • 9-valued logic system
    • ‘U’ – Uninitialized
    • ‘X’ – Forcing Unknown
    • ‘0’ – Forcing 0
    • ‘1’ – Forcing 1
    • ‘Z’ – High impedance
    • ‘W’ – Weak unknown
    • ‘L’ – Weak 0
    • ‘H’ – Weak 1
    • ‘-’ – Don’t care

If forcing and weak signal are

tied together, the forcing signal

dominates.

Useful in modeling the internal

operation of certain types of

ICs.

In this course we use a subset

of the IEEE values: X10Z

01/07/2003 UAH-CPE/EE 422/522 AM 43

Resolution Function for IEEE 9-valued

01/07/2003 UAH-CPE/EE 422/522 AM 44

AND Table for IEEE 9-valued

01/07/2003 UAH-CPE/EE 422/522 AM 45

AND Function for std_logic_vectors