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Instructions: ANSWER ALL QUESTIONS in the answer booklets provided. If you make any

assumptions, clearly state them in your answer booklet.

Materials Allowed: Course textbook, course lecture notes, ENCS approved electronic calcula-

tors.

Location: H539-1

Time: 19:00-22:00

Question 1: [20 points]

The multiply-and-accumulate operation finds use in many digital signal applications. Digital sig-

nal processors often include a dedicated instruction as part of their instructions sets which per-

form the operation. Consider the following three address instruction:

MAC source1, source2, source3/destination

This instruction will perform the operation:

source3/destination <= (source1 x source2) + source3/destination

In other words, the MAC (the mnemonic for “multiply-and-accumulate”) instruction multiplies

the two specified source operands and adds to result to the third source which also acts as the final

destination.

(a) Identify all the addressing modes used in the following instruction:

MAC #NUM, (R0)+, R1

(b) The sequence of control steps to perform an instruction fetch using the single-bus internal

CPU organization shown in Figure 1 are:

T0: BUS <= PC, MAR <= BUS, sel_temp = 1, F = ADD, ld_result = 1.

T1: READ = 1, MDR <= data_out from memory (this implies ld_mdr = 1 and sel_mdr = 1),

BUS <= RESULT, PC <= BUS.

T2: BUS <= MDR, IR <= BUS.

In the above, we assume that main memory will respond (for a READ or a WRITE) within one

clock cycle.

(i) What advantage does the multiplexer at the input of the MDR offer in terms of program execu-

tion speed?