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TUTORIAL
Fundamentals of Phase Locked Loops (PLLs)
FUNDAMENTAL PHASE LOCKED LOOP ARCHITECTURE
A phase-locked loop is a feedback system combining a voltage controlled oscillator (VCO) and a phase comparator so connected that the oscillator maintains a constant phase angle relative to a reference signal. Phase-locked loops can be used, for example, to generate stable output high frequency signals from a fixed low-frequency signal.
Figure 1A shows the basic model for a PLL. The PLL can be analyzed as a negative feedback system using Laplace Transform theory with a forward gain term, G(s), and a feedback term, H(s), as shown in Figure 1B. The usual equations for a negative feedback system apply.
(B) STANDARD NEGATIVE FEEDBACK CONTROL SYSTEM MODEL
(A) PLL MODEL
ERROR DETECTOR LOOP FILTER VCO
DETECTORPHASE^ CHARGEPUMP FEEDBACK DIVIDER FO = N FREF
(A) PLL MODEL
ERROR DETECTOR LOOP FILTER VCO
DETECTORPHASE^ CHARGEPUMP FEEDBACK DIVIDER FO = N FREF
Figure 1: Basic Phase Locked Loop (PLL) Model
The basic blocks of the PLL are the Error Detector (composed of a phase frequency detector and a charge pump ), Loop Filter , VCO , and a Feedback Divider. Negative feedback forces the error signal, e(s), to approach zero at which point the feedback divider output and the reference frequency are in phase and frequency lock, and FO = NFREF.
Referring to Figure 1, a system for using a PLL to generate higher frequencies than the input, the VCO oscillates at an angular frequency of ωO. A portion of this signal is fed back to the error detector, via a frequency divider with a ratio 1/N. This divided down frequency is fed to one input of the error detector. The other input in this example is a fixed reference signal. The error detector compares the signals at both inputs. When the two signal inputs are equal in phase and frequency, the error will be constant and the loop is said to be in a “locked” condition.
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PHASE FREQUENCY DETECTOR (PFD)
Figure 2 shows a popular implementation of a Phase Frequency Detector (PFD), basically consisting of two D-type flip flops. One Q output enables a positive current source; and the other Q output enables a negative current source. Assuming that, in this design, the D-type flip flop is positive-edge triggered, the possible states are shown in the logic table.
D1 Q
CLR
CLR D2 Q
V+
V −
HI
HI
+IN
− IN
DELAY
UP
DOWN
CP OUT
I
I
U
U
U
PFD
CP
D1 Q
CLR
CLR D2 Q
V+
V −
HI
HI
+IN
− IN
DELAY
UP
DOWN
CP OUT
I
I
U
U
U
PFD
CP
(A) OUT OF FREQUENCY LOCK AND PHASE LOCK
(B) IN FREQUENCY LOCK, BUT SLIGHTLY OUT OF PHASE LOCK
0
+I
+I 0
(A) OUT OF FREQUENCY LOCK AND PHASE LOCK
(B) IN FREQUENCY LOCK, BUT SLIGHTLY OUT OF PHASE LOCK
0
+I
+I 0 UP 1 0 0
DOWN 0 1 0
**CP OUT
UP 1 0 0
DOWN 0 1 0
**CP OUT
+IN − IN
OUT 0
+I
− I
(C) IN FREQUENCY LOCK AND PHASE LOCK
Figure 2: Phase/Frequency Detector (PFD) Driving Charge Pump (CP)
Consider now how the circuit behaves if the system is out of lock and the frequency at +IN is much higher than the frequency at –IN, as shown in Figure 2A. Since the frequency at +IN is much higher than that at –IN, the UP output spends most of its time in the high state. The first rising edge on +IN sends the output high and this is maintained until the first rising edge occurs on –IN. In a practical system this means that the output, and thus the input to the VCO, is driven higher, resulting in an increase in frequency at –IN. This is exactly what is desired. If the frequency on +IN were much lower than on –IN, the opposite effect would occur. The output at OUT would spend most of its time in the low condition. This would have the effect of driving the VCO in the negative direction and again bring the frequency at –IN much closer to that at +IN, to approach the locked condition.
Figure 2B shows the waveforms when the inputs are frequency-locked and close to phase-lock. Since +IN is leading –IN, the output is a series of positive current pulses. These pulses will tend to drive the VCO so that the –IN signal become phase-aligned with that on +IN. When this occurs, if there were no delay element between U3 and the CLR inputs of U1 and U2, it would be possible for the output to be in high-impedance mode, producing neither positive nor negative current pulses. This would not be a good situation.
The "N counter," also known as the N divider, is the programmable element that sets the relationship between the input and output frequencies in the PLL. The complexity of the N counter has grown over the years. In addition to a straightforward N counter, it has evolved to include a prescaler , which can have a dual modulus. This structure has grown as a solution to the problems inherent in using the basic divide-by-N structure to feed back to the phase detector when very high-frequency outputs are required. For example, let’s assume that a 900 MHz output is required with 10 Hz spacing. A 10 MHz reference frequency might be used, with the R- Divider set at 1000. Then, the N-value in the feedback would need to be of the order of 90,000. This would mean at least a 17-bit counter capable of dealing with an input frequency of 900 MHz. To handle this range, it makes sense to precede the programmable counter with a fixed counter element to bring the very high input frequency down to a range at which standard CMOS will operate. This counter, called a prescaler , is shown in Figure 3B.
However, note that using a standard prescaler as shown reduces the system resolution to F1×P. This issue can be addressed by using a dual-modulus prescaler which has the advantages of a standard prescaler, but without loss of resolution. A dual-modulus prescaler is a counter whose division ratio can be switched from one value to another by an external control signal. It's use is described shown in Figure 4.
**=
, THEREFORE**
DUAL MODULUS PRESCALER ÷ P / P + 1
Figure 4: Adding a Dual Modulus Prescaler to the PLL
By using the dual-modulus prescaler with an A and B counter, one can still maintain output resolution of F1. However, the following conditions must be met:
- The output signals of both counters are High if the counters have not timed out.
- When the B counter times out, its output goes Low, and it immediately loads both counters to their preset values.
- The value loaded to the B counter must always be greater than that loaded to the A counter.
Assume that the B counter has just timed out and both counters have been reloaded with the values A and B. Let’s find the number of VCO cycles necessary to get to the same state again.
As long as the A counter has not timed out, the prescaler is dividing down by P + 1. So, both the A and B counters will count down by 1 every time the prescaler counts (P + 1) VCO cycles. This means the A counter will time out after ((P + 1) × A) VCO cycles.
At this point the prescaler is switched to divide-by-P. It is also possible to say that at this time the B counter still has (B – A) cycles to go before it times out. How long will it take to do this: ((B – A) × P).
The system is now back to the initial condition where we started.
The total number of VCO cycles needed for this to happen is :
N = [A × (P + 1)] + [(B – A) × P] = AP + A + BP – AP = BP + A.
Therefore, FOUT = (FREF /R) × (BP + A), as in Figure 4.
There are many specifications to consider when designing a PLL. The input RF frequency range and the channel spacing determine the value of the R and N counter and the prescaler parameters.
The loop bandwidth determines the frequency and phase lock time. Since the PLL is a negative feedback system, phase margin and stability issues must be considered. Spectral purity of the PLL output is specified by the phase noise and the level of the reference- related spurs.
Many of these parameters are interactive; for instance, lower values of loop bandwidth lead to reduced levels of phase noise and reference spurs, but at the expense of longer lock times and less phase margin.
Because of the many tradeoffs involved, the use of a PLL design program such as the Analog Devices' ADIsimPLL™ allows these tradeoffs to be evaluated and the various parameters adjusted to fit the required specifications. The program not only assists in the theoretical design, but also aids in parts selection and determines component values.
OSCILLATOR/PLL PHASE NOISE
A PLL is a type of oscillator, and in any oscillator design, frequency stability is of critical importance. We are interested in both long-term and short-term stability. Long-term frequency
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET, fm , (LOG SCALE)
1 f
1 f 2
1 f 3
"WHITE" PHASE NOISE (BROADBAND)
"FLICKER" PHASE NOISE
1 f CORNER FREQUENCY
INTEGRATE PHASE NOISE OVER BANDWIDTH TO GET RMS TIME JITTER
f (^) OUTPUT
Figure 6: Phase Noise in dBc/Hz Versus Frequency Offset from Output Frequency
Note that the phase noise curve is somewhat analogous to the input voltage noise spectral density of an amplifier. Like amplifier voltage noise, low 1/f corner frequencies are highly desirable in an oscillator.
In some cases, it is useful to convert phase noise into time jitter. This can be done by basically integrating the phase noise plot over the desired frequency range. (See Tutorial MT-008, Converting Oscillator Phase Noise to Time Jitter). The ability to perform this conversion between phase noise and time jitter is especially useful when using the PLL output to drive an ADC sampling clock. Once the time jitter is known, its effect on the overall ADC SNR can be evaluated. The ADIsimPLL™ program (to be discussed shortly) performs the conversion between phase noise and time jitter.
FRACTIONAL-N PHASE LOCKED LOOPS
Fractional-N PLLs have been utilized since the 1970s. As has been discussed, the resolution at the output of an integer-N PLL is limited to steps of the PFD input frequency as shown in Figure 7A, where the PFD input is 0.2 MHz.
Fractional-N allows the resolution at the PLL output to be reduced to small fractions of the PFD frequency as shown in Figure 7B, where the PFD input frequency is 1 MHz. It is possible to generate output frequencies with resolutions of 100s of Hz, while maintaining a high PFD frequency. As a result the N-value is significantly less than for integer-N.
REF DIVIDER R
PFD FILTER VCO
N COUNTER
FREF
F 1 FOUT 10MHz R =
0.2MHz
N = 4501
900.2MHz
REF DIVIDER R
PFD FILTER VCO
"N" COUNTER
FREF
F 1 FOUT 10MHz R =
1MHz 900.2MHz N =900.
"N" = N (^) INTEGER +
N (^) FRACTION NMODULUS^ = 900 +^
NFRACTION 5
FOUT = FREF × (N/R)
(A) INTEGER N
(B) FRACTIONAL N
Figure 7: Integer-N Compared to Fractional-N Synthesizer
Since noise at the charge pump is multiplied up to the output at a rate of 20logN, significant improvements in phase noise are possible. For a GSM900 system, the fractional-N ADF offers phase noise performance of –103 dBc/Hz, compared with –93 dBc/Hz for the ADF integer-N PLL.
Also offering a significant advantage is the lock-time improvement made possible by fractional- N. The PFD frequency set to 20 MHz and loop bandwidth of 150 kHz will allow the synthesizer to jump 30 MHz in less than 30 μs. Current base stations require two PLL blocks to ensure that LOs can meet the timing requirements for transmissions. With the super-fast lock times of fractional-N, future synthesizers will have lock time specs that allow the two “ping-pong” PLLs to be replaced with a single fractional-N PLL block.
The downside of fractional-N PLLs is higher spurious levels. A fractional-N divide by 900. (See Figure 7B) consists of the N-divider dividing by 900 80% of the time, and by 901 20% of the time. The average division is correct, but the instantaneous division is incorrect. Because of this, the PFD and charge pump are constantly trying to correct for instantaneous phase errors. The heavy digital activity of the sigma-delta modulator, which provides the averaging function, creates spurious components at the output. The digital noise, combined with inaccuracies in matching the hard-working charge pump, results in spurious levels greater than those allowable by most communications standards. Only recently have fractional-N parts, such as the ADF4252, made the necessary improvements in spurious performance to allow designers to consider their use in traditional integer-N markets.
REFERENCES
- Mike Curtin and Paul O'Brien, "Phase-Locked Loops for High-Frequency Receivers and Transmitters"
Part 1, Analog Dialogue , 33-3, Analog Devices, 1999 Part 2, Analog Dialogue , 33-5, Analog Devices, 1999 Part 3, Analog Dialogue , 33-7, Analog Devices, 1999
- Roland E. Best, Phase Locked Loops, 5th Edition , McGraw-Hill, 2003, ISBN: 0071412018.
- Floyd M. Gardner, Phaselock Techniques, 2nd Edition , John Wiley, 1979, ISBN: 0471042943.
- Dean Banerjee, PLL Performance, Simulation and Design, 3rd Edition , Dean Banerjee Publications, 2003, ISBN: 0970820712.
- Bar-Giora Goldberg, Digital Frequency Synthesis Demystified , Newnes, 1999, ISBN: 1878707477.
- Brendan Daly, "Comparing Integer-N and Fractional-N Synthesizers," Microwaves and RF , September 2001, pp. 210-215.
- Adrian Fox, "Ask The Applications Engineer-30 (Discussion of PLLs)," Analog Dialogue , 36-3, 2002.
- Hank Zumbahlen, Basic Linear Design , Analog Devices, 2006, ISBN: 0-915550-28-1. Also available as Linear Circuit Design Handbook , Elsevier-Newnes, 2008, ISBN-10: 0750687037, ISBN-13: 978-
- Chapter 4.
- Walt Kester, Analog-Digital Conversion , Analog Devices, 2004, ISBN 0-916550-27-3, Chapter 6. Also available as The Data Conversion Handbook , Elsevier/Newnes, 2005, ISBN 0-7506-7841-0, Chapter 6.
- Walt Kester, "Converting Oscillator Phase Noise to Time Jitter," Tutorial MT-008, Analog Devices
- Design Tool: ADIsimPLL, Analog Devices, Inc.
- Analog Devices PLL Product Portfolio: http://www.analog.com/pll
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