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The University of Alabama in Huntsville Electrical & Computer Engineering Department CPE 426 01 Final Exam Solution Spring 2002
Name: _______________________________
- (5 points) What kind of hardware element will be inferred by a synthesis tool from the following model? Answer: a latch, since the behavior is level sensitive
library ieee; use ieee.std_logic_1164.all;
entity WIDGET is Port (A, B : in SIGNED (0 to 2); CLK, RESET : in std_logic; Z : out SIGNED(0 to 2)); end WIDGET;
architecture EXAMPLE of WIDGET is begin process (CLK, RESET) begin if (RESET = โ1โ then) Z <= โ0โ;` elsif (CLK = โ1โ) then Z <= A nor B; end if; end process; end EXAMPLE;
- (9 points) Draw the transistor-level diagram of a CMOS three-input NAND gate.
VCC
GND
x y z
x
y
z
f
- (12 points) Modify the following VHDL model by adding a parameter that sets the number of flip-flops in the counter. Also, add an input which is loaded with an asynchronous load input signal which is active low.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity UPCOUNT is generic (N : integer); port ( CLOCK, RESETN, E : in std_logic; LD : in std_logic; LD_INPUT : in std_logic_vector (N-1 downto 0); Q : out std_logic_vector (N-1 downto 0)); end UPCOUNT;
architecture BEHAVIOR of UPCOUNT is signal COUNT : std_logic_vector (N-1 downto 0); begin process (CLOCK, RESETN, LD) begin if RESETN = โ0โ then COUNT <= (OTHERS => โ0โ); if (LD = โ0โ) then COUNT <= LD_INPUT; elsif (CLOCKโevent and CLOCK = โ1โ) then if E = โ1โ then COUNT <= COUNT + 1; else COUNT <= COUNT; end if; end if; end process Q <= COUNT;
end BEHAVIOR;
b. (6 points) Derive an ASAP schedule.
-- (^) *****
A B
/
+
E F
+
+
A B C D
X
Y
D C F
B
W
S
S
S
c. (6 points) Derive an ALAP schedule.
-- (^) *****
A B
*** /**
+
E F
+
*** +**
A B C D
X Y
D
C F
B
W
S
S
S
- (10 points) Derive a schedule using the freedom-directed method for the VHDL code above, using the following hardware constraint; all operations are done in an ALU module and there are two ALU modules available.
Operation Earliest ASAP Latest ALAP Range 1 1 4 4 2 1 4 4 3 2 5 4 4 1 4 4 5 1 3 3 6 2 4 3 7 3 5 3 8 1 4 4 9 2 5 4
For two ALUs,
Step 1 {1, 2, 4, 5, 8} schedule 5, 1 Step 2 {2, 4, 8, 6} schedule 6, 2 Step 3 {4, 8, 3} schedule 4, 8 Step 4 {3, 7, 9} schedule 7, 3 Step 5 {9} schedule 9
--
A B
*** /**
+
E F
+
*** +**
A B C D
X Y
D C F
B
W
1
2
3
4
5
6
7
8
9
S
S
S
S
S
- (4 points) List the four types of paths that must be considered when doing timing analysis of sequential circuits.
__________inputs to inputs of storage elements_________________________
__________inputs to outputs________________________________________
__________outputs of storage elements to inputs of storage element_________
__________outputs of storage elements to outputs_______________________
- (15 points) Create a VHDL entity named mux4to1 that represents a 4-to-1 multiplexer which has an architecture which uses a case statement to represent the functionality of the multiplexer. Create a second entity and its accompanying architecture that represents a 16-to-1 multiplexter by using at least four instances of the mux4to1 entity.
library ieee; use ieee.std_logic_1164.all;
entity MUX4TO1 is port ( DATA_IN : in std_logic_vector (3 downto 0); SEL : in std_logic_vector (1 downto 0); DATA_OUT : out std_logic); end MUX4TO1;
architecture CASEMUX of MUX4TO1 is begin process (DATA_IN, SEL) begin case SEL is when "00" => DATA_OUT <= DATA_IN(0); when "01" => DATA_OUT <= DATA_IN(1); when "10" => DATA_OUT <= DATA_IN(2); when "11" => DATA_OUT <= DATA_IN(3); when others => DATA_OUT <= 'X'; end case; end process; end CASEMUX;
library ieee; use ieee.std_logic_1164.all; use work.all;
entity MUX16TO1 is port (DATA_IN : in std_logic_vector (15 downto 0); SEL : in std_logic_vector (3 downto 0); DATA_OUT : out std_logic); end MUX16TO1;
architecture STRUCT of MUX16TO1 is component MUX4TO1C port (DATA_IN : in std_logic_vector (3 downto 0); SEL : in std_logic_vector (1 downto 0); DATA_OUT : out std_logic); end component; for all : MUX4TO1C use entity MUX4TO1(CASEMUX); signal INTERNAL : std_logic_vector (3 downto 0); begin U1 : MUX4TO1C port map (DATA_IN(3 downto 0), SEL(1 downto 0), INTERNAL(3)); U2 : MUX4TO1C port map (DATA_IN(7 downto 4), SEL(1 downto 0), INTERNAL(2)); U3 : MUX4TO1C port map (DATA_IN(11 downto 8), SEL(1 downto 0), INTERNAL(1)); U4 : MUX4TO1C port map (DATA_IN(15 downto 12), SEL(1 downto 0), INTERNAL(0)); U5 : MUX4TO1C port map (INTERNAL(3 downto 0), SEL(3 downto 2), DATA_OUT); end STRUCT;
- (8 points) If the NRE costs for FPGA and CBIC circuits are $25,000 and $166,000, respectively, and the cost of individual parts for FPGA and CBIC circuits are $20 and $6, respectively, what is the break-even manufacturing volume for these two types of circuits?
Let x be the number of parts. Then,
$25,000 + $20X = $166,000 + $6x 14x = 141, x = 10071
- (2 points) _____Standard cells____________________ are primitives that are all the same height and varying widths.
- (3 points) The three types of primary design units are _entities, configurations, and packages.
