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Central Processing Unit (CPU)
- CPU is the heart and brain
- It interprets and executes machine level instructions
- Controls data transfer from/to Main Memory (MM) and CPU
- Detects any errors
- In the following lectures, we will learn:
- Instruction representation
- Data transfer mechanism between MM and CPU
- The internal functional units of two different CPU architectures
- How these units are interconnected
- How a processor executes instructions
Instruction Representation
- CPU operation is determined by the instruction it executes
- Collection of these instructions that a CPU can execute forms its Instruction Set
- An instruction is represented as sequence of bits, for example:
- Instruction is divided into fields
- Opcode indicates the operation to be performed, eg., 92 above indicates a copy operation โ we need two operands โ one source and other destination
- Opcode represents
- nature of operands (data or address), operand 1 is address and operand 2 is data
- mode (register or memory), operand 1 is memory, and operand 2 is immediate data 1001 0010 0000 0011 1011 1011 1000 0001 9 2 0 3 B B 8 1 Opcode Operand1 Operand
Simple Instruction Set
Assume we have a processor whose Instruction Set consists of four machine language instructions
- Move from a memory location to a data register in CPU
- Move from a data register in CPU to a memory location
- Add the contents of a memory location to a data register
- Stop Suppose our program for Z = X + Y looks like: Move X, D Add Y, D Move D0, Z Stop This program is coded into machine instruction and suppose is loaded into memory starting at location $0000 0000 move $0000 0000 add move stop
- How does the CPU know which instruction to execute?
- There is a dedicated register in CPU called Program Counter (PC) that points to the memory location where next instruction is stored Therefore, at start PC = $0000 0000
- Instruction is in Main Memory โ it is to be transferred
(fetched) to CPU to be executed
- CPU has an Instruction Register (IR) that holds the instruction
- What kind of instruction is to be executed?
- CPU has its own Instruction Interpreter (Decoder)
- Followed by Instruction execution
- Next instruction follows. PC is incremented by length of
instruction just completed
CISC and RISC
Reduced Instruction Set Computers (RISC)
- Performs simple instructions that require small number of basic steps to execute (smaller S)
- Requires large number of instructions to perform a given task โ large code size (larger N)
- more RAM is needed to store the assembly level instructions
- Advantage: Low cycles per second โ each instruction is executed faster in one clock cycle (smaller R)
- Example: Advanced RISC Machines (ARM) processor Complex Instruction Set Computers (CISC)
- Complex instructions that involve large number of steps (larger S)
- Fewer instructions needed (smaller N) โ small code size
- Commands represent more closely to high-level languages
- Less RAM required to store the program
- Disadvantage: High cycles per second
- Example: Motorola 68000 processor, Intel x
General Purpose Register (GPR)Architecture
Its functional units are: Data Registers : D0, D1, D2,..., D7 for arithmetic operations โ holds any kind of data Address Registers : A0, A1, A 2 ,..., A7 serve as pointers to memory addresses Working Registers : several such registers โ serve as scratch pads for CPU Program Counter (PC) holding the address in memory of the next instruction to be executed. After an instruction is fetched from memory, the PC is automatically incremented to hold the address of, or point to, the next instruction to be executed. Instruction Register (IR) holds the most recently read instruction from memory while it is being decoded by the Instruction Interpreter. Memory Address Register (MAR) holds the address of the next location to be accessed in memory. Memory Buffer Register (MBR or MDR) holds the data just read from memory, or the data which is about to be written to memory. Buffer is referring to temporarily holding data. Status Register (SR) to record status information
Program Execution
Fetch Cycle:
- Processor fetches one instruction at a time from successive memory locations until a branch/jump occurs.
- Instructions are located in the memory location pointed to by the PC
- Instruction is loaded into the IR
- Increment the contents of the PC by the size of an instruction Decode Cycle:
- Instruction is decoded/interpreted, opcode will provide the type of operation to be performed, the nature and mode of the operands
- Decoder and control logic unit is responsible to select the registers involved and direct the data transfer. Execute Cycle:
- Carry out the actions specified by the instruction in the IR
Execution for add D1,D2 in a GPR processor
MAR ๏ PC MDR ๏ M[MAR] IR ๏ MDR D2 ๏ D1 + D PC ๏ PC + 2 Fetch Decode Execute
Execution for add X,D0 in a GPR processor
MAR ๏ PC MDR ๏ M[MAR] IR ๏ MDR MAR ๏ IR (X) PC ๏ PC + 2 Fetch Decode MDR ๏ M[MAR]^ Execute D0 ๏ MDR + D Address X extracted from IR Contents of Address X transferred to MDR Contents of Address X added to D
GPR CPU Type equation here. MBR MAR PC Increment Interpreter IR Register File 0 1 2 3 ALU CPU (^) Memory Data bus Address bus Memory Control 16 bit 8 bit
Accumulator (Acc)Architecture
- Its functional units are same as GPR architecture, except there is only ONE register โ accumulator (Acc) โ instead of the Register File Ex: Z = X + Y Move contents of location X to Acc Add contents of location Y to Acc Move from Acc to location Z Stop
- All operations and data movements are on this single register
- Most of the instructions in the instruction set require only one Operand
- Destination and Source are implicitly Acc
- Leads to shorter instructions but program may be slower to execute since there are more moves to memory for intermediate results (to free Acc)
- May lead to inefficiency
Accumulator Architecture CPU MBR MAR PC Increment Interpreter IR Acc ALU CPU (^) Memory Data bus Address bus Memory Control 16 bit 10 bit
GPR vs Acc Let the following instructions be allowed: For GPR machine (with 4 data reg)
- Move ๐
๐, ๐
๐ ; ๐
๐ โ ๐
๐ Move ๐
๐
, M[X] ; ๐
๐
โ M[X]
Move M[X] , ๐
๐
; M[X] โ ๐
๐
, M[X] ; ๐
๐
๐
+ M[X]
Add ๐
๐
๐
๐
๐
๐
- Sub ๐
๐, M[X] ; ๐
๐ โ ๐
๐ โ M[X] Sub ๐
๐
๐
๐
๐
๐
- Mult ๐
๐, ๐
๐ ; ๐
๐ โ ๐
๐ โ ๐
๐
- Stop For Accumulator machine
- Add x ; ๐ด๐๐ โ ๐ด๐๐ + M[X]
- Sub x ; ๐ด๐๐ โ ๐ด๐๐ โ M[X]
- Mult x ; ๐ด๐๐ โ ๐ด๐๐ โ M[X]
- LD x ; ๐ด๐๐ โ M[X]
- ST x ; M[X] โ ๐ด๐๐
- Stop
Note that M[X] = x
GPR vs Acc Assembly Program for a <- (x + y) * (x โ y) For GPR machine (with 4 data reg) Move ๐ท0, ๐ Add ๐ท0, ๐ Move ๐ท1, ๐ Sub ๐ท1, ๐ Mult ๐ท0, ๐ท Move ๐ด, ๐ท Stop For Accumulator machine LD X ADD Y ST C LD X SUB Y MULT C ST A STOP
