PMOS Structure, Operation, and Equations, Exams of Electronic Circuits Analysis

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n -type substrate

p -type source

& drain

gate oxide

metal contacts

Basic PMOS structure

p -channel device ( n - and p -type regions reversed.)

oxide

width (

W )

oxide

gate

gate length (distance from source

to drain) – currently

as small as 20 nm.

Critical dimensions

width: typical L to 10 L

( W/L ratio is important)

oxide thickness: typical 1 - 10 nm.

width (

W )

oxide

gate

length (

L

)

oxide thickness ( t ox

)

source

drain

width (

W )

The PMOS capacitor

Same as the NMOS capacitor, but with n -type substrate.

In the substrate, there are lots of electrons (majority carriers), and

relatively few holes (minority carriers).

C

ox

body gate

contact

substrate (body)

Apply a positive voltage

to the gate – electron

accumulation.

Apply a (smallish)

negative voltage to the

gate. Electrons are pushed

away and a few holes are

attracted – carrier

depletion.

–^ +

v GB

body gate

contact

substrate (body)

–^ +

v GB

body gate

contact

substrate (body)

v

GB

electron accumulation

V

T

< v

GB

carrier depletion

v

GB

< V

T

inversion –

hole sheet forms.

(Note: V T is negative.)

Through the application of the gate voltage, we can control what is

happening with carriers under the gate.

Summary of PMOS capacitor operation

Creating a hole inversion layer connects the source to the drain. The

PMOS is “on”.

For now, we connect the source to the body and apply the controlling

voltage between the gate and the source. This is OK for the time

being, but we will have to revisit the issue of the body connection

later. With the drain also at ground, the inversion layer (channel) is

uniform between source and drain.

i D

electrons drain

source

gate

n

p p

v GS

< V

T

hole inversion layer

–^ +

body

If v DS is kept small, the current flow is

“ohmic” – like a resistor. R DS depends on

the how much gate voltage is applied

(determining the hole concentration in

the inversion layer) and the physical

dimensions of the PMOS.

i D

v DS

R

DS

–^ +

v DS

i D

holes

drain

source

gate

n

p p

v GS

< V

T

hole inversion layer

–^ +

body

–^ +

v DS

i D

holes

drain

source

gate

n

p p

v GS

< V

T

hole inversion layer

–^ +

body

But as v DS becomes more negative, the

hole concentration at the drain is reduced

• the channel is no longer uniform and it

is becoming more resistive. The i-v curve

becomes non-linear, becoming parabolic.

i D

= K

2 ( v GS

V

T

) v DS

v

2

DS

K =

μC ox

W

L

v GS

> V

T i D = 0 off

v GS

< V

T

_v DS

v GS_

– V

T

i D = K [ 2 ( v GS

– V

T ) v DS

- v DS

2 ]

ohmic or

linear

v GS

< V

T

v DS < v GS

– V

T

i D = K [ v GS

– V

T

]

2 saturation

Summary of PMOS equations

K =

μC ox

W

L

V

T

Note the equations are identical

to the NMOS equations. For a

PMOS, v GS and v DS are both

negative and the current flows

from source to drain.

The PMOS substrate (body)

In applying the drain voltage to make the drain current flow, why did we

use a negative value for v DS ? It would seem that a positive v DS would be

OK.

The reason becomes clear when we consider the p-n junction formed by

the drain and the substrate.

If the substrate is at ground potential and we apply a positive voltage to

the drain, the p-n junction there would be forward-biased – probably

with a very large voltage – and huge currents would flow from the drain

into the substrate. The junction would likely be burned out.

The PMOS substrate rule: The substrate (body) should be connected to

the highest voltage in the circuit – usually the positive power supply.

Then the source and drain must both be at the same or lower voltages,

and it will be impossible to forward-bias the diodes.

v DS

i D

holes

drain

source

n

p p

v GS

< V

T

hole inversion layer

body

PMOS example

v GS

v DS

i D

V

DD

R

D

V

G

–10 V

–4 V

10 kΩ

VTP = –1V

Kp = 0.5 mA/V

2

Essentially the same circuit but with a different

value of RD.

From the previous examples, we can be certain

that the PMOS is on. Guess saturation again, and

we get the same value for the current.

i D

= K

p (

v GS

− V

Tp )

2

0.5 mA/V

2

) [

4 V − 1 V

]

2

= 4.5 mA

v DS

= V

DD

• i D

R

D =^ −^10 V^ +^

4.5 mA ) (

10 kΩ )

= 35 V

Oh no! The drain-to-source voltage is not more negative than VGS – VT ,

so it can’t be in saturation. In fact, 35 V is not even possible given the

power supplies. The PMOS must be operating in ohmic.

i D

= K

p [

V

GS

− V

Tp )

V

DS

− V

2

DS ]

v DS

= V

DD

• i D

R

D

i D

v DS

− V

DD

R

D

EE 230 PMOS – 17

v DS

− V

DD

R

D

= K

p [

V

GS

− V

Tp )

v DS

− v

2

DS ]

Blerk!

Plug into your calculator and solve. Or do it the old-fashioned way —

start by re-arranging:

v

2

DS

[

V

GS

− V

Tp )

K

p

R

D

]

v DS

V

DD

K

p

R

D

Plug in values:

v

2

DS

{

2 [

− 4 V − (− 1 V) ]

−

1

(

0.5 mA/V

2

) (

10 kΩ )

}

v DS

−

− 10 V

(

0.5 mA/V

2

) (

10 kΩ )

= 0

v

2

DS

−6.2 V

v DS

+ 2 V

2

= 0

Equating the resistor current to the drain current:

Solve to get vDS = –0.341 V or vDS = –5.86 V. The larger value is not

consistent with the PMOS being in ohmic. So with vDS = –0.341 V, the

drain current is:

i D

v DS

− V

DD

R

D

−0.341 V − (− 10 V)

10 kΩ

= 0.97 mA

PMOS example

v GS

v DS

i D

V

DD

R

D

With NMOS transistor, we saw that if the gate is tied

to the drain (or more generally, whenever the gate

voltage and the drain voltage are the same), the

NMOS must be operating in saturation. The same is

true for PMOSs. In the circuit at right, vDS = vGS ,

and so vDS < vDS – VTp will always be true for VTp < 0.

With the PMOS in saturation:

i D

= K

p (

v GS

− V

Tp )

2

= K

p (

v DS

− V

Tp )

2

and,

v DS

= i D

R

D

− V

DD

Insert the second into the first:

i D

= K

p (

i D

R

D

− V

DD

− V

Tp )

2

Expand:

i D

= K

p [

i

2

D

R

2

D

V

DD

+ V

Tp )

i D

R

D )^

V

DD

+ V

Tp )

2

]

+10 V

1 kΩ

VTP = –1V

Kp = 0.5 mA/V

2

Re-arrange:

i

2

D

V

DD

+ V

Tp )

R

D

K

p

R

2

D

i D

[

V

DD

+ V

Tp

R

D

]

2

Plug in values:

i

2

D

−

2 [

10 V + (− 1 V) ]

1 kΩ

1

(

0.5 mA/V

2

) (

1 kΩ )

2

i D

[

10 V + (− 1 V)

1 kΩ

]

2

= 0

i

2

D

− ( 20 mA) i D

• 81 mA

2

= 0

Solve to give: iD = 5.64 mA or iD = 14.36 mA. The larger voltage is too

big — in that case vDS = +4.36, which is not compatible for a PMOS.

So the drain current is iD = 5.64 mA and the corresponding drain-to-

source voltage is vDS = –4.36 V. All is good.