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Advanced Logic Design: A University Course on HDL-based Digital Design - Prof. Buren Wells, Study Guides, Projects, Research of Electrical and Electronics Engineering

A part of the university of alabama in huntsville (uah) cpe/ee 422/522 advanced logic design course material. It covers the motivation for using hardware description languages (hdl) in digital design, the benefits of hdl-based design, and an overview of the design flow. The document also introduces the uah library of soft cores and outlines the project-based approach of the course.

Typology: Study Guides, Projects, Research

Pre 2010

Uploaded on 07/22/2009

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CPE/EE 422/522
Advanced Logic Design
Electrical and Computer Engineering
University of Alabama in Huntsville
28/05/2003 UAH-CPE/EE 422/522 AM 2
Motivation
Benefits
of HDL-based design
Portability
Technology independence
Design cycle reduction
Automatic synthesis and
Logic optimization
… But, the gap between
available chip complexity
and design productivity
continues to increase
Design productivity
21% / year
Chip Complexity
58% / year
28/05/2003 UAH-CPE/EE 422/522 AM 3
Educators Mission
Educate future generations of designers
Emphasis on hierarchical IP core design
Design systems, not components!
Understand hardware/software co-design
Understand and explore design tradeoffs between
complexity, performance, and power consumption
Design a soft processor/micro-controller core
28/05/2003 UAH-CPE/EE 422/522 AM 4
UAH Library of Soft Cores
Microchip’s PIC18 micro-controller
Microchip’s PIC16 micro-controller
Intel’s 8051
ARM Integer CPU core
FP10 Floating-point Unit
pf3
pf4
pf5
pf8
pf9
pfa

Partial preview of the text

Download Advanced Logic Design: A University Course on HDL-based Digital Design - Prof. Buren Wells and more Study Guides, Projects, Research Electrical and Electronics Engineering in PDF only on Docsity!

CPE/EE 422/

Advanced Logic Design

Electrical and Computer Engineering

University of Alabama in Huntsville

28/05/2003 UAH-CPE/EE 422/522 AM 2

Motivation

  • Benefits

of HDL-based design

  • Portability
  • Technology independence
  • Design cycle reduction
  • Automatic synthesis and

Logic optimization

  • … But, the gap between

available chip complexity

and design productivity

continues to increase

Design productivity 21% / year

Chip Complexity 58% / year

28/05/2003 UAH-CPE/EE 422/522 AM 3

Educators Mission

  • Educate future generations of designers
    • Emphasis on hierarchical IP core design
    • Design systems, not components!
    • Understand hardware/software co-design
    • Understand and explore design tradeoffs between

complexity, performance, and power consumption

⇒ Design a soft processor/micro-controller core

28/05/2003 UAH-CPE/EE 422/522 AM 4

UAH Library of Soft Cores

  • Microchip’s PIC18 micro-controller
  • Microchip’s PIC16 micro-controller
  • Intel’s 8051
  • ARM Integer CPU core
  • FP10 Floating-point Unit
28/05/2003 UAH-CPE/EE 422/522 AM 5

Design Flow

ReferenceReference ManualManual

InstructionInstruction Set AnalysisSet Analysis

DpthDpth &&CntrCntr DesignDesign

VHDL ModelVHDL Model

VerificationVerification

ASM TestASM Test ProgramsPrograms

MPLAB IDEMPLAB IDE

iHex2RomiHex2Rom

Synthesis&Synthesis& ImplementationImplementation

CC

ProgramsPrograms

C CompilerC Compiler

J

28/05/2003 UAH-CPE/EE 422/522 AM 6

Benefits

  • Proposed project-based

approach encompasses

the whole engineering

cycle

  • Put together knowledge in

digital design, HDLs,

computer architecture,

programming languages

  • State-of-the-art devices
  • Work in teams

Specification

Design

Modeling

Simulation & Verification

FPGA

Implementation

Measurements (Compl.&Perf.&Power)

Design Improvements

28/05/2003 UAH-CPE/EE 422/522 AM 7

PIC18 Greetings

28/05/2003 UAH-CPE/EE 422/522 AM 8

Outline

Review of Logic Design Fundamentals

  • Combinational Logic
  • Boolean Algebra and Algebraic Simplifications
  • Karnaugh Maps
  • Combinational- Circuit Building Blocks
28/05/2003 UAH-CPE/EE 422/522 AM 13

Boolean Algebra

  • Basic mathematics used for logic design
  • Laws and theorems can be used to

simplify logic functions

  • Why do we want to simplify logic functions?
28/05/2003 UAH-CPE/EE 422/522 AM 14

Laws and Theorems of Boolean Algebra

28/05/2003 UAH-CPE/EE 422/522 AM 15

Laws and Theorems of Boolean Algebra

28/05/2003 UAH-CPE/EE 422/522 AM 16

Simplifying Logic Expressions

  • Combining terms
    • Use XY+XY’=X, X+X=X
  • Eliminating terms
    • Use X+XY=X
  • Eliminating literals
    • Use X+X’Y=X+Y
  • Adding redundant terms
    • Add 0: XX’
    • Multiply with 1: (X+X’)

YCin XCin XY

(X'YCin XYCin) (XY'Cin XYCin) (XYCin' XYCin )

Cout X'YCin XY'Cin XYCin'XYCin

28/05/2003 UAH-CPE/EE 422/522 AM 17

Theorems to Apply to Exclusive-OR

X ⊕ 0 = X

X ⊕ 1 =X '

X ⊕X= 0

X ⊕X'= 1

X ⊕ Y=Y⊕ X (Commutative law)

( X⊕ Y)⊕Z=X⊕(Y⊕Z )(Associative law)

X( Y⊕ Z)=XY⊕ XZ (Distributive law)

( X⊕Y)'=X⊕Y'=X'⊕Y=XY+X'Y '

28/05/2003 UAH-CPE/EE 422/522 AM 18

Karnaugh Maps

  • Convenient way to simplify logic

functions of 3, 4, 5, (6) variables

  • Four-variable K -map
    • each square corresponds to one

of the 16 possible minterms

  • 1 - mintermis present;

0 (or blank) – minterm is absent;

  • X – don’t care
    • the input can never occur, or
    • the input occurs but the output is not specified
  • adjacent cells differ in only one value =>

can be combined

Location

of minterms

28/05/2003 UAH-CPE/EE 422/522 AM 19

Sum-of-products Representation

  • Function consists of a sum of prime implicants
  • Prime implicant
    • a group of one, two, four, eight 1s on a map

represents a prime implicant if it cannot be combined

with another group of 1s to eliminate a variable

  • Prime implicant is essential if it contains a 1

that is not contained in any other prime implicant

28/05/2003 UAH-CPE/EE 422/522 AM 20

Selection of Prime Implicants

Two minimum

forms

28/05/2003 UAH-CPE/EE 422/522 AM 25

Six Variable Karnaugh Map

CD
EF
CD
EF
CD
EF
CD
EF

AB=00 AB=

AB=10 AB=

28/05/2003 UAH-CPE/EE 422/522 AM 26

Designing with NAND and NOR Gates (1)

  • Implementation of NAND and NOR gates is easier

than that of AND and OR gates (e.g., CMOS)

28/05/2003 UAH-CPE/EE 422/522 AM 27

Designing with NAND and NOR Gates (2)

  • Any logic function can be realized using only

NAND or NOR gates => NAND/NOR is complete

  • NAND function is complete –

can be used to generate any logical function;

  • 1: a I (a | a) = a | a’ = 1
  • 0: {a I (a | a)} | {a I (a | a)} = 1 | 1 = 0
  • a’: a | a = a’
  • ab: (a | b) | (a | b) = (a | b)’ = ab
  • a+b: (a | a) | (b | b) = a’ | b’ = a + b
28/05/2003 UAH-CPE/EE 422/522 AM 28

Conversion to NOR Gates

  • Start with POS (Product Of Sums)
    • circle 0s in K-maps
  • Find network of OR and AND gates
28/05/2003 UAH-CPE/EE 422/522 AM 29

Conversion to NAND Gates

  • Start with SOP (Sum of Products)
    • circle 1s in K-maps
  • Find network of OR and AND gates
28/05/2003 UAH-CPE/EE 422/522 AM 30

Tristate Logic and Busses

  • Four kinds of tristate buffers
    • B is a control input used to enable and disable the output
28/05/2003 UAH-CPE/EE 422/522 AM 31

Data Transfer Using Tristate Bus

28/05/2003 UAH-CPE/EE 422/522 AM 32

Combinational-Circuit Building Blocks

  • Multiplexers
  • Decoders
  • Encoders
  • Code Converters
  • Comparators
  • Adders/Subtractors
  • Multipliers
  • Shifters
28/05/2003 UAH-CPE/EE 422/522 AM 37

Synthesis of Logic Functions Using Muxes

w 3

w 3

f

w 1

0

w 2

(a) Modified truth table (b) Circuit

w 1 f

0

w (^) 2

w 1 w 2 w 3 f 0 0 0 0 1 1 1 1

w (^) 3

28/05/2003 UAH-CPE/EE 422/522 AM 38

Decoders: n-to-

n

Decoder

  • Decode encoded information: n inputs, 2n^ outputs
  • If En = 1, only one output is asserted at a time
  • One- hot encoded output
    • m-bit binary code where exactly one bit is set to 1

w (^) n – 1

n inputs

Enable En

2 n outputs

y (^) 0

y 2 n (^) – 1

w

y w ...ww En

y w '...ww'En

y w '...w'wEn

y w '...w'w'En

n

n

n

n

n 1 10

−^ −

28/05/2003 UAH-CPE/EE 422/522 AM 39

Decoders: 2-to-4 Decoder

w 1 y 0

0

w 0

(c) Logic circuit

w 1

w 0

x x

En

y 1

y (^) 2

y (^) 3

y (^) 0

y (^) 1

y 2

y (^) 3

En

w 0

En

y 0 w 1 y 1 y 2 y 3

(a) Truth table

(b) Graphic symbol

28/05/2003 UAH-CPE/EE 422/522 AM 40

Decoders: 3-to-8 Using 2-to-

w 2

w 0 y 0 y 1 y 2 y 3

w 0

En

y 0 w 1 y 1 y 2 y 3

w 0

En

y 0 w 1 y 1 y 2 y 3

y 4 y 5 y 6 y 7

w 1

En

28/05/2003 UAH-CPE/EE 422/522 AM 41

Decoders: 4-to-16 Using 2-to-

w 0

En

y 0 w 1 y 1 y 2 y 3

y 8 y 9 y 10 y 11

w 2

w 0 y 0 y 1 y 2 y 3

w 0

En

y 0 w 1 y 1 y 2 y 3

w 0

En

y 0 w 1 y 1 y 2 y 3

y 4 y 5 y 6 y 7

w 1

w 0

En

y 0 w 1 y 1 y 2 y 3

y 12 y 13 y 14 y 15

w 0

En

y 0 w 1 y 1 y 2 y 3

w 3

En

28/05/2003 UAH-CPE/EE 422/522 AM 42

Encoders

  • Opposite of decoders
    • Encode given information into a more compact form
  • Binary encoders
    • 2n^ inputs into n-bit code
    • Exactly one of the input signals should have a value of 1,

and outputs present the binary number that identifies which input is

equal to 1

  • Use: reduce the number of bits

(transmitting and storing information)

2 n inputs

w (^) 0

w (^) 2 n (^) – 1

y 0

y (^) n – 1

n outputs

28/05/2003 UAH-CPE/EE 422/522 AM 43

Encoders: 4-to-2 Encoder

w 3 y 1

0

y (^) 0

(b) Circuit

w 1

w 0

w (^) 2

w (^) 1

w 0

y 0 w 2

w 3^ y 1 (a) Truth table

28/05/2003 UAH-CPE/EE 422/522 AM 44

Encoders: Priority Encoders

  • Each input has a priority level associated with it
  • The encoder outputs indicate the active input

that has the highest priority

d

w 0 y 1

d

y 0

z

x

x

x

w 1

x

x

w 2

x

w 3

(a) Truth table for a 4-to-2 priority encoder